Senior Engineer II – VLSI

Alphawave Semi is a design industry-leading, high-speed connectivity solutions for customers in high-growth end markets.

• Data centre
• AI
• 5G wireless infrastructure
• Data networking
• Autonomous vehicles
• Solid-state storage

Our leading-edge technology advances push the boundaries of wired connectivity capabilities, enabling data to travel faster, more reliably, and using lower power.

Powering next-generation technologies, we serve Tier-One customers in North America, Asia Pacific, Europe, and the UK. Our innovative solutions have repeatedly set industry benchmarks in terms of performance, power consumption, size, and flexibility.

Responsibilities:

• Experience in  deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,….)
• Complex high speed designs for edge computing applications  (3.2G HBM PHY, Processor hardening for PPA analysis)
• Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environments including clear understand of clock domain crossings, Should be able to work closely with Physical Design Teams
• Good knowledge of Functional & DFT modes and constraints, Signal integrity, Good knowledge of de-rates (OCV, AOCV,POCV)
• Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs
• Experience with EDA Tools and Methodologies for STA, STA based ECO, Synthesis – hierarchical synthesis, DFT handling, retiming, clock gating
• Correlating results between STA and GLS with AMS
• Understanding of power management and UPF concepts at Synthesis/PnR/STA domains
• Good scripting skills; experience in Tempus is a plus
• Experience in  deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,….)
• Complex high speed designs for edge computing applications  (3.2G HBM PHY, Processor hardening for PPA analysis)
• Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environments including clear understand of clock domain crossings, Should be able to work closely with Physical Design Teams
• Good knowledge of Functional & DFT modes and constraints, Signal integrity, Good knowledge of de-rates (OCV, AOCV,POCV)
• Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs
• Experience with EDA Tools and Methodologies for STA, STA based ECO, Synthesis – hierarchical synthesis, DFT handling, retiming, clock gating
• Correlating results between STA and GLS with AMS
• Understanding of power management and UPF concepts at Synthesis/PnR/STA domains
• Good scripting skills; experience in Tempus is a plus