- Lead layout design activity and manage delivery of high frequency mixed signal blocks/IPs.
- Minimum 4 years of exp in Analog Layout.
- Minimum education requirement is bachelor’s degree in Electrical Engineering.
- Experience in handling blocks and macros layout towards successful, high-quality, and timely execution.
- Experience with Cadence tools (Virtuoso) and Calibre verification tools like LVS, DRC, Extraction etc.
- Excellent understanding of analog layout concepts and issues.
- Experience with Finfet process and lower nodes like 3nm/5nm/7nm in TSMC foundry.
- Understanding of low parasitic, high frequency design techniques.
- Experience with multiple foundries in lower node.
- SKILL scripting experience.
- Excellent verbal and written communication.
- Strong analytical and debug skills
- Strong priority-resolution capabilities
- Working well in a team environment is imperative in this role.
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