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Senior Engineer II- ASIC design

Senior Engineer II- ASIC design
by Admin on 08-25-2023 at 7:25 pm

Website Alphawave Semi


  • Will be responsible for verification of IP, Block, or Subsystem at Soc Level
  • Generate appropriate documentation for verification
  • Responsible for analyzing/debugging given blocks/tasks in verification
  • Should be able to develop and own the verification environment, verification components developed


  • 8+ years of experience with a Bachelors’/ Master’s degree in the field of Electrical, Electronics, or computer engineering
  • Should have a good understanding of verification flow, challenges, and requirements of functional verification
  • Should have worked on IP level or Block level or SoC level functional verification
  • Skilled in digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy
  • Expert in System Verilog, Verilog, and OVM/UVM verification methodology
  • Should have working experience on AMBA interface protocols (AXI, AHB, APB)
  • Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must
  • Hands-on experience on working one or more of the following protocols is a must – UART, I2C, SPI, QSPI, I3C, eMMC, CAN,
  • Hands-on experience working with one or more of the following protocols is desired – PCIe, USB, DDR, LPDDR, GBE, SATA
  • Experience with Perl, Python or similar scripting languages will be helpful
  • Ability to adapt & learn quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals.
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