Senior Engineer I – ASIC Design

Alphawave Semi is a design industry-leading, high-speed connectivity solutions for customers in high-growth end markets.

• Data centre
• AI
• 5G wireless infrastructure
• Data networking
• Autonomous vehicles
• Solid-state storage

Our leading-edge technology advances push the boundaries of wired connectivity capabilities, enabling data to travel faster, more reliably, and using lower power.

Powering next-generation technologies, we serve Tier-One customers in North America, Asia Pacific, Europe, and the UK. Our innovative solutions have repeatedly set industry benchmarks in terms of performance, power consumption, size, and flexibility.

Responsibilities:

• Perform hands-on physical design and physical verification tasks across projects in advanced process nodes.
• Own project specific ASIC development flow setup and maintenance.
• Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis and LEC for block level and full chip flat/hierarchical designs. Co-ordinate full chip physical design and verification activities.
• Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debug and implementing fixes in the physical design database.
• Ensure correct IP and pad-ring integration in block and flat designs.
• Mentoring junior PD/PV team members and overseeing their tasks.

Requirements:

• Personality – Team player, good written and verbal communication, quick learner
• Education – B. Tech /M. Tech in Electronics Engineering
• Experience – Minimum 5+ years
• Skill set – Should have worked on advanced FinFET node designs.
•  Experience with Cadence PnR/STA tools and Calibre, good scripting/automation skills is a must.