Senior Engineer I – Analog Design

Responsibilities:

• HBM2E SoC analog sub-block design such as DLL, PLL, HBMIO, Clktree, VCDL and DCC
• Block-level architecture selection as per specs
• Design and simulation across pvt to meet specs
• Help in .lib generation and support review
• Post-layout simulations
• Help in Verilog code generation for block owned and validate with schematic
• Signoff on collaterals

Requirements:

• Minimum 3 years of experience in analog circuit design
• Experience in dual patterning FinFET design
• FinFET expertise in TSMC 7nm, GF 14lpp, TSMC 16ffc, GF 22fdxsoi
• Skilled at basics and device physics, with understanding of the following:
• Current mirrors, bandgap reference, Opamp, common source amplifier small signal analysis and various topologies
• Hands-on wrt of each block
• Basics of design constraints, current mirror matching, Opamp types and circuit design, comparator circuit design, bgref circuit design, level shifter circuit design, GPIO driver, pre-driver full custom circuit design, Tx/Rx constraints understanding
• Basic knowledge of the following layouts: antenna checks, antenna failure, latchup issues, ESD constraints and layout rules, ERC-related checks, matching, cross talk, coupling, shielding, guard ring usage, LEF generation, .lib characterization,extraction setup, drc lvs runs switch knowledge, IR drop requirements, EM issues, parasitic matching, parasitic reduction techniques, and static and dynamic IR analysis
• Completed at least one of the following circuit designs >1GHz speed: DLL full circuit design, PLL full chip circuit design, or LVDS/USB/DDR/HBM Full Chip circuit design
• Experience in ADC/DAC circuit design is a plus
• Experience in SerDes circuit design is a plus