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Senior Engineer I – AMS Modeling

Senior Engineer I – AMS Modeling
by Admin on 11-08-2022 at 3:39 pm

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  • Knowledge on System Verilog, Verilog RTL, Verilog AMS and Verilog A
  • Developing behavioral models for Mixed Signal Systems.
  • Familiarity with the Cadence Analog Design Environment (ADE-L), ideally using the AMS simulator
  • Cadence Virtuoso, Spectre circuit simulator, Incisive and AMS simulators experience
  • An understanding of Analog circuit design, transient simulation and analysis
  • Basic understanding of Analog circuits e.g PLLs, DLL, DCC, i/o’s, Bandgap, Oscillators etc
  • Document or otherwise archive developed material for future use or re-use


  • Must possess a minimum of Bachelor’s degree in Electronic Engineering or related program
  • Must possess a 3 to 5 years work experience as a AMS or Modeling or Design engineer role.
  • Experience with different Technology Node (16nm,12nm,7nm, 5nm etc)
  • Experience with different foundry (TSMC, GF, SAMSUNG, SMIC) and design techniques would be an asset.
  • Excellent organizational skills and strong attention to detail
  • Personality – team player, good written and verbal communication, open to new ideas and quick learner
  • Experience – Minimum 3+ years
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