Senior Engineer – DFT

Alphawave Semi is a design industry-leading, high-speed connectivity solutions for customers in high-growth end markets.

• Data centre
• AI
• 5G wireless infrastructure
• Data networking
• Autonomous vehicles
• Solid-state storage

Our leading-edge technology advances push the boundaries of wired connectivity capabilities, enabling data to travel faster, more reliably, and using lower power.

Powering next-generation technologies, we serve Tier-One customers in North America, Asia Pacific, Europe, and the UK. Our innovative solutions have repeatedly set industry benchmarks in terms of performance, power consumption, size, and flexibility.

Responsibilities:

• Defining DFT Architecture or Spec at block and SoC level
• Leading DFT activities by working with project stake holders to meet the goals
• DFT Implementation in RTL/Netlist at block and SoC level as per specs for Memory BIST, Boundary Scan, Scan and IP test
• Pattern generation and simulation in RTL, netlist at block and SoC level
• Develop and validate DFT mode SDC constraints for Synthesis and STA
• Project flow setup and execution
• Post-layout simulations at block and SoC level
• Verilog RTL coding and verification for test logic modules
• Experience in planning and tracking DFT activities to closure
• Mentoring and guiding team members on technical front

Requirements:

• Experience in digital design and verification using Verilog, VHDL, SV
• Expertise in SoC level DFT – Memory BIST & Repair, Boundary Scan, Scan Insertion, IP test strategy, IJTAG
• Experience in handling high speed interface and mixed signal IPs for DFT
• Experience in Mentor Tessent, Synopsys or Cadence DFT tool sets
• Skilled in solving DFT design issues in RTL/Netlist and coverage improvements.
• Skilled in ATE pattern delivery and silicon debug
• Hands on in scripting using TCL, Unix shell, Perl
• Strong communication and presentation skills
• Focused and result oriented with eagerness to learn