Senior Emulation Engineer

Must haves:

• Experience with Mentor Veloce, Cadence Palladium, Synopsys Zebu
• Experience in creating transactors for either of the 3 emulation tools
• Experience in porting and debugging of SOC/ Subsystem or module level testbench to emulation platform

Good to have:

• Verification Experience for Block level, Sub System or SOC Level
• Strong experience with Verilog, System Verilog and UVM
• Verification Experience with PCIe Gen 4/ 5, USB 3/ 4
• Verification Experience with Memory controllers DDR4/ 5, LPDDR 4/5, HBM, GDDR6
• Create and execute Test plans targeting Sub – systems and SoC level.
• System level performance analysis, bandwidth, latency across interconnects.
• Experience with Speed Bridge Integration and perform real time testing.
• Experience in Automation and increasing process efficiency.