Senior DV Engineer

We value growth and collaboration in the Digital Design Verification team. We enjoy working together and take pride in supporting each other to deliver results. Our group is fun, dynamic, and social. Those who wish to pursue a career in semiconductors will find many opportunities on this team to learn new skills, be challenged, and take on real responsibilities.

What you’ll do

• Review design specifications and devise verification plan
• Build testbenches and analyze test failures to uncover design bugs
• Take on opportunities to lead, plan, and coordinate tasks with team members
• Perform behavioral modeling of analog circuits
• Facilitate bit-matching of RTL design and MATLAB system models
• Integrate 3rd party VIPs for compliance testing of standard protocols
• Build releases of our design IP for customers
• Support post-silicon validation and bring-up activities
• Work closely with Design, Systems, Analog, FW, and PD teams for final verification closure
• Contribute towards the continuous improvement of verification methodologies and processes

What You’ll Need

• We are open to candidates with experience levels ranging from 2yrs to 10 yrs,
• Constrained-random verification with Systemverilog and UVM
• SerDes PHY, DSP, and Analog Mixed-signal verification experience
• Knowledge in Ethernet and PCIe standards is desirable
• Formal verification, and Power-aware UPF verification techniques
• Tools/Languages – Systemverilog, UVM, Python, Perl, C/C++, GNU Make

“Hybrid work environment”

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

• Great compensation package
• Health Insurance
• Retirement Savings
• Paid time off