Senior DFT Engineer

In this role, as a DFT Engineer, you will work on implementation of test structures and development of methodologies for pattern generation and diagnosis of our eFPGA products. You will work with customers to ensure that all test goals are being achieved in their production as well as provide all the required collateral. Also, you will execute test related activities for our inference accelerator products.

You’ll be working with multiple software teams, deep learning scientists, and hardware designers, to implement the features needed to accelerate the next generation of machine learning algorithms. Must be passionate about being part of an aggressive, venture-backed startup team that is changing chip architecture.  Must be entrepreneurial, innovative problem solver and willing to work hard.

Responsibilities

• Scan pattern generation for eFPGA products
• Develop DFT flow and automations for high-quality production
• Implement and verify DFT solutions
• MBIST implementation
• Interface with contractors or partners
• Development of methodologies for silicon diagnosis
• Collaborate with customer to ensure successful and timely production of silicon
• Clearly communicate and document methods and scripts
• Clearly communicate status throughout the project

Required Experience

• Proven experience in defining strategy and implementation of at least 1 high-volume production SOC
• Proven experience defining design for test requirements for IP
• Proven experience setting-up flows with standard EDA tools
• Experience with ATPG generation, simulation and in silicon debug
• Hand-on experience on scan insertion
• Experience with MBIST insertion and verification
• Deep understanding of how leading DFT industry tools work
• Recent hands-on experience implementing DFT on a significant SOC
• BS/MS EE/CE with 5 or more years of relevant industry experience
• Must be innovative and be able to cater solutions to particular designs
• Must have hands-on experience in scripting languages
• Must have hands-on experience in testbench creation and gate-level simulations with SDF

Preferred Experience

• Understanding of FPGA architectures and how to best test them
• Running logic synthesis and static timing tools