Senior Design Engineer

Are you an experienced VLSI design engineer and highly passionate about your work?

Then you belong with us!

CEVA is looking for you to join our growing VLSI team.

Here in CEVA we are developing state of the art DSP ASIC projects in A.I, Vision, Wireless and Base-stations area. The VLSI team is responsible for the planning and the implementation of DSP cores and accelerators which are a part of many future products.

As you experienced Design Engineer you will be responsible for 

• Writing micro-architecture specifications of modules.
• RTL Verilog coding of modules. Writing design assertions.
• Support of verification teams in coverage closure and the debug of modules and sub-systems.
• Work with cross functional teams – Architecture, Verification, BE and SW.

• Minimum 2.1 Honors degree in Electronic Engineering, Computer Science or a related field.
• 6+ years of experience in digital ASIC design, RTL coding (Verilog/VHDL, SVA) and coverage closure.
• Good understanding of design techniques for performance, power and/or area optimizations.
• Team player with excellent communication abilities to liaise with customers and other CEVA design offices.

Desirable Criteria:

• Good working knowledge of the back end physical design flow for complex ASIC designs.
•  Expertise in the design of processors, memory sub-systems, AMBA bus systems.
•  Experience with SOC design.
•  Assembly level coding for verification and IP integration.
•  Use of the synthesisable subset of SystemVerilog for design.
• Experience in state of the art verification techniques, including assertion-based, constrained random and metric-driven verification.
• Knowledge of TCL, PERL and Python scripting languages.
• Experience in linting and clock-domain crossing tools and techniques.