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Senior ASIC Verification Engineer

Senior ASIC Verification Engineer
by Admin on 05-19-2023 at 3:21 pm

Responsibilities

Verification: Work on USB3.2 IP UVM based verification environment set up, testcase creation and debug, regression and coverage work

Requirements

1. 1~5 years ASIC verification experience

2. BS or MS in Electrical Engineering

3. Skilled with System Verilog and UVM

4. Familiar with coverage oriented random test

5. Hands on experience with RTL debug

6. Familiar with shell/perl/makefile

7. Experience with PCIE/USB/SATA/ethernet or other connectivity protocols is a plus

8. Good communication and problem solving skills

For careers related questions and applications, please contact hr@corigine.com.

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