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Senior ASIC Verification Engineer

Senior ASIC Verification Engineer
by Admin on 11-16-2022 at 11:36 am

Website Synopsys

As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop testplan, testbench and testcases to verify mixed signal (digital and analog) designs.


  • Generates verification specifications.
  • Establishes test bench design and test cases.
  • Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
  • Generates documentation for testplans, verification environments, and usage.
  • Participate in evaluation and troubleshooting of digital and mixed signal designs.

Key Qualifications:

  • Candidate should have a clear desire to learn and explore new technologies.
  • Demonstrates good communication skills in English.
  • Demonstrates good analysis and problem-solving skills.
  • Prior knowledge CAD tool for development.
  • Working knowledge of Verilog and SystemVerilog.
  • Working experience with scripting languages.

Preferred Experience:

  • Knowledge of high speed interface protocols such as HBM, DDR, DFI;
  • Understanding of verification methodology such as UVM is a plus
  • Typically requires a minimum of 3 years of related work experience.
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