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Senior ASIC Verification Engineer

Senior ASIC Verification Engineer
by Admin on 07-31-2023 at 2:46 pm


  • Verification: Work on USB3.2 IP UVM based verification environment set up, testcase creation and debug, regression and coverage work


  • 1~5 years ASIC verification experience
  • BS or MS in Electrical Engineering
  • Skilled with System Verilog and UVM
  • Familiar with coverage oriented random test
  • Hands on experience with RTL debug
  • Familiar with shell/perl/makefile
  • Experience with PCIE/USB/SATA/ethernet or other connectivity protocols is a plus
  • Good communication and problem solving skills

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