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Senior ASIC Design Engineer

Senior ASIC Design Engineer
by Admin on 11-07-2022 at 3:43 pm

Website Mixel

About the Job

  • Develop a thorough understanding of system-level design specifications
  • RTL Coding/Synthesis of the digital part of Mixed Signal IPs
  • Develop behavioral models for the analog parts of Mixed Signal IPs
  • Working with the verification team to develop advanced test plans
  • Working with the mixed signal team on the co-simulation and verification of the IPs
  • Hardware verification of the digital module using cutting edge FPGA kits

Job Requirements

  • B.Sc. or M.Sc. in Electronics Engineering
  • 3+ Years of experience in VLSI Digital Design
  • Strong knowledge of Verilog RTL design/simulation, gate verification techniques is a plus
  • ASIC/FPGA design flows including RTL synthesis, and timing sign-off
  • Experience with clock domain crossing and reset architecture
  • Working knowledge of Shell, Perl, and TCL scripting
  • Unix/Linux operating system
Apply for job

To view the job application please visit mixel.com.

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