Senior Analog Design Engineer
Website Synopsys
Job Description and Requirements
Analog and Mixed Signal Design Engineer
Join us as an analog and mixed-signal design engineer in the PLL design team. Our designs enable the next generation of datacenters, automobiles and communications networks. You will work on system-level and circuit-level PLL design in the latest FINFET CMOS technology nodes. PLL designs will support high-speed Serdes designs including PCI-Express, Ethernet, CPRI, and other applications at rates up to 112Gbps, 224Gbps and beyond.
Responsibilities and Duties:
- Circuit-level PLL design and PLL top-level modeling and simulation
- Design of analog circuits such as VCOs, charge pumps and voltage regulators
- Custom circuit design in deep-submicron and FINFET CMOS technologies
- Design of high-speed digital circuits such as dividers and clock distribution paths
- Schematic entry and spice simulation of custom circuits
Qualifications and Experience:
- MSEE with 2+ years or PhD with 1+ year experience in CMOS analog and mixed-signal circuit design
- Detailed knowledge of PLL loop operation and design
- Previous design experience of PLL circuit components such as VCO’s, charge-pumps, regulators and high-speed dividers
- Design experience in deep-submicron and FINFET CMOS technologies
- Hspice, Finesim or similar spice-type simulators
- Schematic entry in Synopsys Custom Designer or similar tools
- Knowledge of digital timing in PrimeTime and/or Nanotime is an asset
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