In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest process nodes. Working from SERDES standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
- Review SERDES standards to develop novel transceiver architectures and sub-block specifications.
- Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets.
- Work across project and department teams to streamline design and verification strategies to ensure overall design quality, efficiency and performance.
- Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
- Present and review simulation data from internal project teams. Present results externally at industry panels or at customer reviews.
- Document design features and test plans.
- Consult on the overall electrical characterization of the SERDES IP product. Review customer silicon data for design enhancements. Propose solutions for post-silicon design updates.
- Ph.D. with 3+ years, or M.Sc. with 5+ years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of study.
- In depth familiarity with transistor level circuit design – sound CMOS design fundamentals.
- Detailed design experience with one, and familiarity with several other SERDES sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC.
- Familiarity with custom digital design (i.e. high-speed logic paths).
- Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc).
- Understanding of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.) as well as ESD issues (i.e. circuit techniques, layout).
- Experience with tools for schematic entry, physical layout, and design verification.
- Understanding of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
- Excellent communication, presentation, and documentation skills.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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