RTL IP Design

Job Description

• Proven success in development of complex ASIC, FPGAs and products.
• Demonstrated capability to design major blocks involving ASIC, IPs, logic, and FPGAs.
• Excellent logic developer in Verilog / System Verilog.
• Aware of ASIC design flow. Experience with frontend design tools (Xcelium/Incisive, LINT tools, Genus/Design-Compiler, STA with Tempus/Primetime, power analysis); expert in at least one of these areas. Exposure to backend tools a plus.
• Relevant experience in some major IPs and protocols, such as SERDES, PCIe and DDR4, and ASIC IP integration in general. Expert in at least one such area.
• Understands DFT, BIST, other DFx methodologies.
• Great scripting skills (Python, Bash, etc.)
• Familiarity with verification methodologies and emulation or prototyping experience helpful.
• Excellent problem-solving and debug skills. Comfortable researching IP, firmware, compiler, and systems domains as needed.