RTL / Digital Designer

Blue Cheetah Analog Design Inc. is a growing, technology start-up headquartered in Sunnyvale, California. Our mission is to generate state-of-the-art in package die-to-die semiconductor IP solutions for the rapidly growing chiplet ecosystem. We accomplish this by providing high performance chiplet interface semiconductor IP to our global customers allowing them to reshape their product roadmaps to a more agile and cost effective chiplet based approach. Join our team to help usher in the chiplet era of semiconductor-based products.

We provide a professional benefits package including medical, dental, vision, 401K plan with company match as well as generous holiday & vacation leave. Join a team where your impact to the collective success will be clear and the big company politics do not exist.

[Note: We do not expect anyone to have all the listed skills and encourage those with some to apply]

Job Overview:

•  Design and implement the digital portions of high-performance, state-of-the-art integrated circuits and their IPs using SystemVerilog and higher-level languages.

Job Description:

•  Participate in all phases of digital design including:
  •   architecture definition
  •   functional specification creation
  •   RTL coding
  •   test insertion
  •   design verification
  •    logic synthesis
  •    timing closure
  •    formal verification
  •    design reviews

•  Collaborate closely with analog, verification, physical design, and firmware engineers to ensure your digital design is complete, correct, and performs as intended.
•  Interact with 3^rd-party IP and VIP providers and with Blue Cheetah customers to ensure our requirements and our deliverables are met.

Minimum Qualifications:

•  BS, MS, or PhD in electrical engineering or computer science.
•  5+ years of relevant industry experience
•  Strong, fundamental understanding of digital design techniques and RTL coding styles and practices
• Experience with Clock Domain Crossing (CDC)
•  In-depth knowledge of SystemVerilog.
•  STA experience including SDC generation, timing analysis and timing closure.
•  DFT experience including scan insertion, ATPG vector generation, JTAG, iJTAG, BIST, MBIST, PRBS generation and checking, and an understanding of manufacturing test needs and how to meet them.
•  Working knowledge of industry standard scripting languages like Tcl, Python, Perl, etc.
•  Working knowledge of revision control systems preferably Git, bug tracking software.

Preferred Qualifications:

•  Experience with PHY-level IP, their protocols and design techniques.
•  Knowledge of low-power design techniques and experience with UPF/CPF.
•  Knowledge of digital PnR tools and their flows to enable smooth handoff
•  Experience supporting silicon test and debug.