RF SoC Design Engineer

Job Responsibilities:

Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital post-processing will include down-sampling and decimation filter structures. Some examples of the synchronization that will be required are below:

1) Coarse alignment of 32 clock phases that are generated from single master clock. These clock phases drive 32 ADC channels that feed the digital post-processing.

2) The digital post-processing filters fed by the 32 ADC channel outputs will be highly parallelized. The final output will be a down-sampled and decimated stream of data originating from the 32 ADC channels. Design and verification of the synchronization of the parallelized digital processing blocks is needed.

3) Synchronization of all enable signals for the RFSoC subsystems: PLL, DAC, ADC, calibration engines for the ADC subsystem, and digital post-processing.

Desired Experience:

– Knowledge of synchronization procedures and capabilities with synchronization tools for RFSoC systems

– Experience using Cadence design tools especially tools used for RFSoC timing such as Tempus Timing Signoff Solution and Quantus Extraction Solution. Experience with comparable tools from other vendors such as Synopsys is also acceptable, but final validation of all projects will use Cadence vendor tools.

– 3+ years of RFSoC design with focus on system timing and validation

– Multi-Tile Synchronization for multiple channels of DAC and ADC for phased array applications

– Clock distribution of a common clock within an RFSoC system and eventually across multiple RFSoC systems