R&D Engineer, Staff

Job Overview

Part of the rapidly expanding Hardware-Analytics and Test (HAT) business unit, R&D Engineer, Staff. This technical role is responsible for HDG’s (Hardware Development Group) Physical Design methodology setup to ensure overall productivity improves in terms of cycle time and man-months for the Silicon Lifecycle management Ips. This includes ensuring automated (synopsys EDA flow based) flow setup for SLM IP blocks with appropriate backend flow. The person need to be a expert of physical design with innovative mindset and automation skills. Work will include working with Analog and Digital teams together for setting up the right PD methodology for both Front end and backend.

Responsibilities and Duties

• Responsible for Physical design for MSIPs for appropriate methodology
• Hands on with custom automations around Synopsys EDA flow PD
• Work out innovative design methodologies to overcome challenges
• Understand AMS Ips and ensure best cycle time for execution by enabling backend flow
• Analyse pros and cons of different flow for IP integration and customer SOC flow

Qualifications

• BS or MS degree in Electrical Engineering/Computer Science/Computer Engineering.
• 8 to 11 years of experience in the fields of Analog/Mixed Signal design for leading edge technologies
• Innovation mindset with automation in SKILL , Perl , Python , C++
• Deep expertise with Synopsys backend flow
• Ability to work with cross functional team spread across different geographies.

Preferred Skills

• Demonstrated experience with Physical Design and methodology expertise
• Understanding latest foundry PDKs and their technical collaterals as required by the Physical design teams including their usage in design and layout
• Thorough knowledge of Physical design flow with digital top SOC integration methodology
• Closely work with Analog layout team by reviewing and enabling Layout methodology (automations) for Analog+Digital integration

Location:  To be hired for Bangalore or Bhubaneswar