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R&D Engineer, Sr I

R&D Engineer, Sr I
by Admin on 06-22-2022 at 2:00 pm

Website Synopsys

Job Description

Emulation group in Synopsys delivers several products such as HAPS, Zebu Server. These products are widely used in the industry for implementation of HDL designs in FPGA prototyping & emulation and debugging of ASICs using FPGAs.  Zebu & HAPS delivers high performance emulation solution taking advantage of commercial FPGSs & innovation in FPGA-based emulation & prototyping software. These software innovations enable users with faster compile, advanced debug including native integration with Verdi, power testing, power aware emulation & prototyping, simulation acceleration and hybrid emulation. Looking for a R&D engineer in emulation & prototyping Lowpower/debug R&D compiler team in Bangalore for the following role and with the given background/skill sets.

Roles and responsibility:

  • A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for low power starting from UPF & HDL parsing, synthesis, logic mapping & optimization, partitioning till FPGA bitstream generation
  • The person is expected to Gather requirement and functional specifications, design and implement efficient data structures and algorithms in C/C++.
  • Work with CAE team in test planning, execution, and customer support.
  • Maintain and support existing product and features.

Expected background and skill:

  • B.Tech /M.Tech in CS/EE from a reputed institute.
  • Sound understanding in data structures, graph algorithms and C/C++ programming multithreading parallel programming on Windows/Unix.
  • Familiarity in digital logic design.
  • Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis is a plus
  • Working understanding of FPGA design tools and flows is a plus.
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