Will be involved in developing software tools for advanced chip design platforms.
The responsibilities also include engaging with customers in understanding their ASIC design requirements for nano-technology process nodes and assisting them in adopting Cadence design platform and helping them in performing successful tapeouts of their System-on-chip designs using the same.
The job will also involves presenting and demonstrating relevant Cadence technologies and carrying out product evaluations, workshops, training and competitive replacement campaigns.
- The candidates should have strong in-depth P&R design experience in COT or ASIC area.
- Experience and ability to get solutions in Floor plan, Power Planning/Analysis, CTS, timing optimization/analysis, signal integrity and DFM issues (DRC & Antenna) is a MUST. Strong interest and understanding of design methodologies are required.
- Need to have good knowledge on VDSM (40nm and below) processes issues.
- Good verbal and written presentation are must.
- Hands-on Cadence Encounter experience is a big plus.
- Minimum master degrees in EE or CS.
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To view the job application please visit cadence.wd1.myworkdayjobs.com.