Principal Solution Engineer

Description

As an Alphawave Principal Solution Engineer within the IP Solutions organization, you are responsible for partnering with our most valuable customers to design complex IP subsystems utilizing Alphawave bleeding edge IP. In this role, you will oversee all aspects of the Alphawave IP product line during engagements with our customers. This includes pre-sale customer requirements, industry standard trends and customization. You will engage with R&D team and marketing team to draft IP specification and requirements to satisfy our customer applications and improve the IP integration experience. You will also be required to solve complex Subsystem usage and track implementation issues during execution.

Responsibilities include: 

• Directing Technical Communication to customers during the SoC lifecycle, working directly with Customer architect, SoC leads
• Implementation of complex IP subsystems including the design additional blocks as necessary to meet customer specific requirements
• Responsible for contributing to the authoring of the associated Subsystem documentation such as user guides, application notes and white papers that promote the Subsystems’ ease of use, or address specific challenges in its implementation
• You will have regular contact with external customers and internal cross-functional teams
• Participate in design specification, verification plan, code, and coverage reviews
• Proactively engaging with customers during SoC integration, debug designs in simulation, emulation, and silicon debug
• Alphawave Customer Success Sponsor
• Occasional travel will be required

Education and Experience: 

• Bachelor’s and/or Master’s degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science
• Minimum of 7 years relevant experience in ASIC/SoC design including RTL coding in Verilog, logic and clock tree synthesis, static timing analysis, equivalence checking, design validation
• Full understanding of SoC design methodologies and tools
• Domain knowledge of the following interface protocols:
  • PCI Express – Gen2, Gen3, Gen4, Gen5, Gen6
  • Ethernet Physical Layer and Fiber Channel applications and standards
  • Die-to-Die Interfaces
• General knowledge of different modulations formats (PAM, NRZ) and optical transceivers are high desirable
• Have experienced multiple ASIC/SoC tape-outs from concept to full production
• Ability to build technical leadership through influence and drive a heterogeneous team toward common goals
• Technically creative, results oriented, with the ability to manage multiple tasks efficiently including customer support issues and priorities
• Strong communication skills and ability to interact with customers as well as peers
• Adaptability to fast moving, changing environment with constant challenge