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Principal Memory Design Engineer

Principal Memory Design Engineer
by Admin on 08-11-2023 at 2:12 pm

  • Full Time
  • Sheffield, UK
  • Applications have closed

sureCore Ltd is a low power SRAM IP company and has developed market leading low power technology. Now actively productising and marketing this technology an opportunity has arisen for a dynamic experienced SRAM designer to join the team. The company has recently launched an “Application Centric SRAM” design service which is gaining market traction in the Augmented Reality/AI/ML markets. This entails developing bespoke low power SRAM to precisely match a customers requirements and embodies all aspects from specification development and signoff to test chip design and silicon evaluation.

Working closely with the Silicon Architect and the engineering team the role will involve undertaking many and varied engineering activities within sureCore and the individual will have the opportunity to make a significant impact. It is expected that the successful candidate will bring their expertise to bear on all aspects of product development.

The individual will have a deep understanding of low power SRAM transistor level design, and verification. A significant part of the role will include development of automated flows so proficiency with Python would be a significant asset. A high level appreciation of DVFS and SoC level power management techniques would also be useful.

A key aspect of the role is ensuring that sureCore SRAM is robust and with adequate margins at agreed corners. This will entail gaining a deep understanding of the low power architectures and that the characterisation and verification regimes allow the SRAM to meet the agreed specifications. More customer engagements are demanding implementation in advanced process nodes including 16nm, 10nm and 7nm FinFET processes. Experience of these would be preferred.

The successful candidate will have a strong SRAM and compiler design background with considerable industrial experience and will be able to demonstrate a thorough understanding of the issues related to IP delivery.

  • Work closely with the silicon architect to agree product specifications
  • Undertake transistor level design, simulation and layout using industry standard tooling
  • Development of automated layout and verification flows
  • Design margin analysis and guard band provision
  • Simulation data analysis
  • High sigma statistical analysis
  • Design methodology development and optimisation
  • Layout verification – DRC & LVS
  • Identification and submission of patentable circuit/architectural design features
  • At least 10 years’ experience of SRAM design
  • Experience in SRAM verification
  • Experience of low power SRAM compiler design
  • Experience of Python coding or evidence of strong scripting skills
  • Experience of low power SRAM design in advanced FinFET nodes
  • Understanding of SRAM structure and issues
  • Running commercial EDA tools (Cadence/Mentor) and potential issues
  • Strong understanding of statistical analysis
  • Understanding of DFT, yield and DFM issues
  • Experience of taking designs into production
  • Strong analytical and problem-solving skills
  • Ability to plan, coordinate and take responsibility for effective and on time completion of project activities
  • Candidate will be qualified to at least degree level, preferably masters
  • Self motivated and creative with a passion for achieving success and excellence
  • Strong interpersonal and communication skills with infectious enthusiasm and tenacity
  • Excellent organizational skills

Please get in touch at careers@sure-core.com

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