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Principal Design Engineer, Digital ASIC/SoC

Principal Design Engineer, Digital ASIC/SoC
by Admin on 08-31-2022 at 2:50 pm

Website CEVA

Intrinsix Corp., the ASIC and SoC Design Services group of CEVA Inc. in the United States, is seeking an experienced ASIC/SoC/FPGA Lead Digital Design Engineer. You will provide hands-on technical leadership and be a top individual contributor in custom ASIC and complex SoC development projects, including FPGA-based prototyping. You will hold responsibility for, and contribute to, all phases of ASIC/SoC/FPGA development starting from creation of an architectural specification through ASIC/SoC/FPGA sign-off (RTL to GDSII).

This position can be an on-site/hybrid work model from the Greater Boston/Metrowest area of Massachusetts, or it can be a fully remote position within the United States with occasional domestic travel.

Core Responsibilities:

  • Perform definition of architecture and development of design specifications, defining implementation strategies and tactics to meet aggressive quality, budget, and schedule goals.
  • Foster strong working relationships with colleagues, creating healthy team dynamics and driving projects to on-time completion.
  • Interface with external customers was requested to clarify design requirements and facilitate customer understanding of design challenges.
  • If requested, assist in resource planning to deliver against specifications, schedule, and budget, participating in pre-tapeout evaluation of designs and post-tapeout retrospectives/lessons learned.

Qualifications and Skills:

  • Bachelors/Masters degree in Electrical Engineering with 10+ years of experience in custom ASIC/SoC design and integration.
  • Hands-on knowledge in front-end development phases of the ASIC process (design and synthesis to simulation and debug).
  • Proficient in RTL design, including coding/scripting in C/C++, Verilog, Tcl, Perl, and/or Python.
  • Experience with deep-submicron CMOS technologies, FinFET (sub-22nm), and a wide variety of ASIC/FPGA process technologies.
  • Significant experience with synthesis, static timing analysis (STA), and DFT ASIC vendor sign-off methodologies, including Cadence and Synopsys tool flows and Mentor Calibre.
  • Knowledge of embedded processor architectures (ARM, RISC-V, x86).
  • Comfortable participating in discussions with internal stakeholders, both in-person and in virtual settings (Zoom, Teams, etc.).
  • Familiar with Microsoft Office 365 (Excel, Word, PowerPoint, Outlook, SharePoint, Teams).

Preferred Skills & Experience:

  • Hands-on knowledge in all phases of the ASIC process (spec and design to GDSII hand-off) with previous experience as a technical/project lead.
  • Ability to obtain Confidential or Secret Security Clearance is a plus, as is experience crafting proposals for U.S. government contracts and understanding EAR/ITAR compliance issues for defense-related projects.
  • Residing in the Northeast region of U.S. for occasional commute to the Marlborough, Massachusetts office is a plus, with the ability to work both on-site and from a home office, coordinating with team schedules as requested.
  • Experience working with remote team members and multi-cultural teams a big plus.
  • Comfortable giving technical presentations and leading discussions with internal and external stakeholders, both in-person and in virtual settings (Zoom, Teams, etc.).

Advanced knowledge in any of the following areas is a plus:

  • Experience in the automotive industry with design requirements for functional safety. Wireless/WiFi, Bluetooth, and UWB technologies for telcom and IoT applications.
  • Experience in fixed-point hardware DSP modeling using MATLAB Simulink.
  • Experience in ASIC verification using SystemVerilog and UVM.
  • Cutting-edge manufacturing trends and techniques for high through-put, densely-arrayed ASICs and large, complex SoCs, including advanced node processes and multi-chip silicon packaging technologies such as HSoCs or 3D ICs.
  • Full-chip physical design of multi-million gate/transistor ASICs and complex SoCs, including PNR, custom layout/custom wiring routes, pin assignments, bump pad placement, I/O locations.

MINIMUM REQUIREMENTS: (Candidates must meet the following criteria to be considered for this position.)

  • Your directly applicable hands-on industry experience must be recent, within the last 2-3 years.
  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related area of study with at least 7 years of industry experience.
  • Must be able to communicate technical concepts fluently in written and spoken English.
  • Must have permanent legal authorization to work in the U.S. without employer sponsorship.*
  • Applicant must be a U.S. Person.**
  • Must currently reside in the United States or relocate back to the country before 10/1/2022.
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To view the job application please visit www.ceva-dsp.com.

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