Principal Design Engineer – AE
Website Cadence
Must to have
- Tape-out experience in RTL2GDS2 (Synthesis, FloorPlan, P&R, Sign-off closure in timing, LEC/CLP, power and physical like DRC/LVS/XOR etc., apart from DFM)
- Strong timing & CTS fundamentals
- Good debugging skills
- Scripting (TCL &/Perl etc.,)
- Attitude towards working with outside India customer programs (Primarily Asia Pacific & North American regions)
- Ability to handle different spectrum of designs like smaller to complex
- Work independently / taking the ownership
Preferred
- Hands on expertise in top level integration is preferred.
- Low power exposure (writing CPF & devising LP implementation strategies)
- Advanced node experience like 10nm, 7nm or 5nm
- Knowledge of DFT
- Communication & Leadership
- Need to exhibit strong leadership & communication skills (verbal / email etc.,)
ASML- Soft revenues & Orders – But…China 49% – Memory Improving