Principal Design Engineer

Cadence is looking for a Principal Design Engineer for Cadence DDR IO team. This person will work on design, verification of high speed transceiver blocks and be responsible for mentoring junior engineers.

Responsibilities will include, but are not limited to the following:

• Analog/ Mixed Signal design engineer for Cadence DDR IO team
• Position is based in Cary, North Carolina
• Role would involve working on design, verification of high speed transceiver blocks
• Role would involve mentoring junior engineers
• Be part of a high-performing world-wide team responsible for delivering memory interface IO libraries to Tier1 OEM/ Semiconductor companies
• Be part of IPG, the fastest growing business unit in Cadence
• Work in Cadence – one of Fortune Magazine’s “100 Best Companies to Work For”.

Requirements

• BSEE, or equivalent with 10 + years; MSEE, or equivalent with 8 – 12 years
• Strong background in the design of Analog and Mixed-Signal circuits like high-speed Transmitter/Receiver, Calibration block, VREF generator, PLL
• Experience in JEDEC memory interfaces like DDRx/LPDDRx/ HBM is highly desired
• Strong in Analog Design fundamentals and IO reliability
• Exposure to scripting languages like Perl, Unix shell or similar languages