Principal Application Engineer (SW verification)

Position Requirements:

4-6 or above years’ experience in the following areas:

1. Design experience in Verilog/VHDL for IP or SoC chip level.

2. Verification with knowledge of System Verilog/VHDL and HDL simulators.

3. Experience of using formal verification, JasperGold experience is a plus.

4. Advanced Verification Methodology like UVM is a plus.

5. Experience of functional safety verification is a big plus.

6. Strong verbal and written communication skills in English.

7. Strong teamwork skills with good human relationship.