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Pr. Physical Design Engineer – AI & eFPGA

Pr. Physical Design Engineer – AI & eFPGA
by Admin on 05-26-2022 at 4:34 pm

Website Flex Logix

Our InferX X1 is the industry’s fastest and most-efficient AI edge inference accelerator that brings AI to high-volume applications, surpassing competitor’s performance at 1/7th size and much lower price. InferX X1 is available as a chip, PCIe board and M.2 board. InferX X1 is working and running YOLOv3 as well as other models today and is ready for production.


  • Generate block level static timing constraints.
  • Build IP floor-plan including pin placement, partitions and power grid.
  • Develop and validate high performance low power clock network guidelines.
  • Perform block level place and route and close the design to meet timing, area and power constraints.
  • Generate and Implement ECOs to fix timing, noise and EM IR violations.
  • Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
  • Participate in establishing CAD and physical design methodologies for correct by construction designs.

Required Experience 

  • 10+ years of Physical Design experience on IP and/or SOC designs.
  • Experience in developing and implementing Power-grid and Clock specifications.
  • Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route.
  • Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools.
  • Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
  • Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
  • Knowledge of Basic HDL languages like Verilog to be able to work with logic design team for timing fixes.
  • Bachelors or Master’s Degree in EE/CS required.

Preferred Experience

  • Familiar with power intent definition, implementation and verification flows.
  • Familiar with of power analysis and optimization methods.
  • Power user of industry standard Physical Design & Synthesis tools.

Must be passionate about being part of an aggressive, venture-backed startup team that is changing chip architecture. Must be entrepreneurial, innovative problem solver and willing to work hard. Must live in Silicon Valley or Austin area and have US citizenship or permanent residency (“green card”), or holding a current H1-B visa.

Flex Logix recruits, employs, trains, compensates and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.

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