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Physical Design Engineer

Physical Design Engineer
by Admin on 06-15-2022 at 2:29 pm

Website TSMC

Responsibilities:

  • Responsible for the physical implementation and tapeout of the test vehicles on TSMC’s most advanced process nodes.
  • Perform the jobs or tasks listed below, but not limited:
    • Physical implementation with netlist2GDS flow including block/SOC level floorplan, low power structure, power ground network, placement, clock tree synthesis, routing, design optimization…
    • Design signoff verification including RC extraction, STA, IREM, DRC, LVS, ERC, VCLP.
    • Timing closure, physical design closure, power/signal integrity closure based on the result of signoff verification.
    • Development and evaluation of the methodology and flow to support most advanced process N5/N4/N3 or beyond.
    • CAD development to support design flow and quality monitoring dashboard for with TCLK/TK, CSH, Python

Requirements:

  • Education:
    • Master’s Degree or above in Electrical Engineering or Computer Science from a top university, VLSI related course & Project preferred.
  • In Depth knowledge on physical design implementation, auto placement and routing, static timing analysis, layout design, physical verification, IREM signoff, cad development.
  • Knowledge on major EDA Tools
  • Good communication skills
  • Strong problem-solving skills
  • Positive, Active, Collaborative, Self-motivated
  • Strong ability to manage demands in a fast-paced environment and diverse cultural styles while being extremely adaptable and flexible.
Apply for job

To view the job application please visit tsmc.taleo.net.

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