IP Release Engineer

About the Role:

You’ll be a silicon engineer and familiar with full custom IP development for the ASIC semiconductor market. As our IP Release Engineer, you’ll be part of the post sales team and will support our global engineering teams. The role will report directly into the IP Maintenance Manager and will be responsible for maintaining and delivering the IP portfolio, meeting both the business and customer expectations

Responsibilities and Duties

• Supporting all stakeholders with an in depth technical knowledge of the full range of products and services supplied.

• Understanding the contents of IP deliverables to customers.

• Ensuring products are up-to-date based on latest foundry PDK updates, bug fixes, patches and improvements based on customer request.

• Managing peer-reviews of IP before delivery to customers.

• The running of layout tools and review of DRC checks for IP quality and control.

• Maintaining a complete overview of all IPs delivered to customers and ensuring all updates and kept to a tight schedule.

• Review as part of maintenance of the existing and future Moortec IPs to ensure high quality level is observed across all the products.

• Capable of resolving design issues and changes to IP when required.

• Proactively identify, suggest and contribute to the development and improvement of customer support process in terms of documentation and IP deliverables.

• Working flexibly and to the needs of the business.

Continuous Professional Development:

• Keep up to date with latest company and customer expectations and provide feedback to all the teams within Moortec.

• To ensure you maintain the highest level of competency for the role employed and where practicable to help develop participate and support you own self development with the full support of the Moortec Teams.

 

Essential Qualifications, Skills and Experience:

• Degree or equivalent in Electronic Engineering or related field.

• 5 + years experience in analogue/mixed signal silicon design.

• Experience of full customer IP development flow from an analogue, digital and layout perspective.

• Having strong semiconductor skills and familiarity within one or more of the following areas:

• Cadence Virtuoso design tools.

• Physical verification flow (Mentor is preferably but not essential).

• Digital ASIC flow (place and route).

• Semiconductor physics.

• Must have good Linux scripting skills.

• A track record of working within a time sensitive commercial environment.

• The role requires the utmost diligence and exceptional attention to detail.

Salary & Benefits:

• Competitive salary

• Supportive career development

• Flexible working

• Company events

• Regular pay reviews

• Company bonus scheme

• 28 days holiday + bank holidays

• Company pension scheme

• Life assurance cover

• HealthShield cash plan (UK)