Mixed Signal Verification Engineer

About the Job

In this position you will play a key technical role in developing and verifying PHY PCS RTL for low power, high-speed, FinFET SERDES hard macros to be used in numerous products from high performance data centers to low power consumer SoCs. You will join a highly collaborative team and your success will have a significant impact on our products.

Candidate should have an interest in all the “Key Qualifications” listed and experience in some of them.

Key Qualifications

• Experience in CMOS circuit design or Mixed signal design verification.
• Understanding of advanced CMOS circuit topologies.
• Understanding in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog and Verilog) for verification.
• Knowledgeable in advanced RTL digital design methodology.
• Understanding of Lint, CDC, Synthesis/P&R/STA, CTS, Xilinx FPGA compiler tools.
• Excellent team player and clear communicator.

Description

• High speed SERDES analog modeling using system Verilog.
• Develop system Verilog/UVM Mix signal test benches, test plans, SV checkers for the verification of RTL and analog functions.
• Contribute to the development and verification of advanced SERDES PCS logic including clock domains crossing, calibration logic, equalization, adaptation, auto-negotiation, BER eye monitor, etc.
• Work closely with the PMA analog design team.
• Interface with customers and assist in integrating the SERDES IP.
• Help improve RTL design and verification methodology.

Education BS required / MS or PhD preferred in electrical engineering or related field.

Base Salary Ranges:

• 1 – 3 years’ experience: $144,000.00 – $200,000.00

We are an equal opportunity employer and value diversity in our workforce. All employment decisions are made on the basis of qualifications, ability, and business requirements.