[Military Service Exemption] RTL Design Engineer

Duties

• Module development including spec definition, macro/micro architecture design, RTL coding, simulation and synthesis

• Maintain and enhance existing RTL blocks and verification environments using scripting tools.

• Collaboration with the software development team

Requirements

• ASIC/SOC/FPGA development experience

• Expertise in design/verification using Verilog HDL and C/C++

• Knowledge of AMBA AXI and memory subsystems

• Possession of EDA tool technology for RTL simulation, debugging, synthesis, and lint/CDC

Preferential treatment

• Python/Perl user skills

• Ability to test bench using SystemVerilog

Working environment and welfare

• Flexible working hours (Core hours: 11:30 AM – 3:30 PM)

• Lunch/dinner support

• Optional welfare benefits of 3 million won per year provided

• Refresh vacation and vacation allowance support

• Health checkups worth 700,000 won per year

• Support for improving development capabilities, including activating in-house seminars.

• Use an English nickname

• Annual salary of 50 million won for new undergraduate students