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Micro Architect RTL Design Engineer- Enterprise Interconnect

Micro Architect RTL Design Engineer- Enterprise Interconnect
by Admin on 06-08-2020 at 5:20 am

Website ARM

Job ID #: 17918
Job Category: Design Engineering
Employment Type: Experienced Professionals
Division: Central Engineering – Systems
Department: Central Engineering – Systems Engineering
Primary Country: USA
Primary Location: Austin (TX)
Additional Country: USA

About the Role

As a Memory System / Interconnect Design Engineer, you will be part of the Systems and Software team focused on next-generation interconnects targeting high-end mobile, networking, and enterprise markets. You will contribute to the specification, microarchitecture and RTL design of high-performance, energy-efficient interconnects. This opportunity is specific to a confidential project, and as part of this small and talented team, you will be able to expand your technical breadth relating to leading-edge interconnects, including multi-chip, IO acceleration, and new memory technologies. In addition, your close collaboration with other Austin-based CPU and System IP engineering teams leads to complete IP solutions to address the performance, power and cost requirements for almost all application markets.

What will I be accountable for?

  • Interconnect Micro-architecture specification and RTL design
  • Verilog RTL logic design and debug
  • Working closely with performance modeling, validation, and implementation teams to meet all functional requirements, performance, power and area goals

What skills, experience and qualifications do I need?

  • Education BS or MS in Electrical Engineering or Computer Engineering
  • Prior RTL design experience is required.
  • An ideal candidate will have at least 2+ and maybe even more than 4+ years of work experience in microprocessor, SoC, memory controller and interconnect IP design.

Technical Attributes

  • Experience with interconnect and bus architectures (with proficiency in IO acceleration, PCIe, system caching, QoS)
  • CPU or compute subsystem memory micro-architecture.
  • Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets
  • Processor system knowledge including basic understanding of SoC systems as well as operating system software

General Attributes

  • Demonstrate enthusiasm, drive and diligence
  • Work well in a team environment
  • Have excellent written and verbal communication skills
  • Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the design center’s success
  • Be able to travel for training or occasional customer interaction
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