We are looking for an energetic and passionate design manager to join our elite and world-class memory solution teams with the exciting opportunity to drive the development of memory compiler solutions, and custom macros of all types for the leading-edge products on market, as well as the implementation of test chips for developing the most advanced process technologies in the world.
- Manage design team by planning and organizing design projects and responding to customer/client’s requests or events as they occur.
- Define power-performance-area (PPA) specifications of SRAM IP with customers and drive architecture, design, verification and testing of SRAM circuits.
- Hands-on design experience on SRAM memory circuits & compiler timing/power characterization, netlist/ layout tiling, design-for-testing (DFT) circuit, and IR/EM analysis.
- Specify silicon test plan and drive debug activity.
- Drive SRAM compiler verification methodology and quality assurance.
- Collaborate closely with cross functional teams across the globe.
- Master or Ph.D. degree in Electrical Engineering or related fields.
- 15 years of experience in memory design and compiler development, including SRAM, Register-File and Emerging Memories.
- Ability to make memory architecture choices based on Performance/Power/Area trade-offs
- Solid understanding of industry-standard EDA tools.
- Familiar with design rules and process of advanced logic process technology (N7 and beyond).
- Good communication skill, team attitude and ability to work under pressure.
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To view the job application please visit tsmc.taleo.net.