- BE/B-Tech (Electronics/ Electrical/ Electronics &Comm) or MSc (VLSI/ Electronics/ Electrical/ Electronics &Comm) or MS or MTech would be preferred
- Worked on SOC level test bench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Test bench generation, test vector creation, simulations, gate level simulations
- Hands on with System Verilog and Assertion based verification methodology
- At least 3years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
- Should be able to work independently and able to guide other team members
- Should have lead a team of 5 or more engineers for at least 1-2 yrs
- Should have experience with Verilog and popular EDA simulation, SV assertions & test bench methodologies.
- Experience in developing complex test bench in System Verilog using OVM/UVM methodology
- Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB3, USB2& Ethernet.
- Experience on formal verification
- Excellent written and oral communication skills are necessary.
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF) would be an added plus
- Experience on System C would be an added plus
Email your resume to email@example.com and mention position/location in the subject.
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