- Experience with Cadence Xcelium/Incisive Simulator, and vManager – Advantage
- Experience with Cloud – Advantage
- Excellent communication skills. Must have ability to communicate complex issues to internal teams and customers in a clear and concise manner.
- Strong debug skills for diagnosing issues
- Proficiency in Unix/Linux scripting languages (ksh/csh/python/perl/etc…)
- Some travel may be required
- Bachelor’s Degree in Electrical or Computer Science Engineering
- Minimum of 5 years’ experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
- Strong background on functional verification fundamentals
- SystemVerilog UVM constrained-random testbench experience
- Understanding of load sharing software like LSF