Lead Design Engineer

Do you enjoy working on cutting-edge technologies that make incredible new things possible? Do you possess the meticulousness and passion for perfection needed to work toward an exceptional outcome? Imagine the possibilities here! At Cadence, we think that innovative ideas may swiftly transform into outstanding goods, services, and client encounters. You may achieve incredible things in your work if you approach it with passion and determination!

This role contributes to the successful execution of semiconductor package design for our high-speed memory interface IPs. This role involves working with our industry esteemed team of engineers across various functions and provides an opportunity to prospective candidate to work with leading- and cutting-edge technology.

As a part of this team, we design and deliver solutions for validating all high-speed Cadence Memory IP solutions for different customer applications. Some of the responsibilities include package substrate design, signal and power integrity, correlating design with manufactured product and process technology.

REQUIREMENTS/ RESPONSIBILITIES:

• Education : BE/BTech or MTech in Electrical/Electronics background.
• Experience : 6+ years of experience in flipchip package design, signal and power integrity analysis
• Strong Experience in co-designing IC-Package-PCB with tradeoffs on SI/PI, thermal constraints
• Collaborate with cross functional teams and customers to guide and deliver best solution for IC-Package-PCB co design.
• Good knowledge in 3D/2D EM simulation tool, electromagnetic theory and transmission line theory
• Strong understanding of die floor planning, IO placement, bump definition, routing feasibility and optimizing the package stackup, BGA ballmap optimization for optimal PCB design
• Knowledgeable about PCB stackup and Fanout strategy
• Knowledgeable about the trade-offs between package cost, design, performance, power, technology, and thermal needs
• Validating the package and PCB in lab
• Provide the management team with a clear and concise update on the program’s status, problems, and risks.
• Experience with various Cadence Allegro tools (APD/SIP, PCB Editor)
• Experience with various modeling tools (Cadence Sigrity PowerSI, ExtractIM, Clarity 3D)
• Perform extraction of S-parameters and package RLGC model.
• Ensure package design is optimized with SI/PI requirements.
• Experience in working with different DRAM protocols, DDR4/5, GDDR6/7, HBM2/3, LPDDR4/5
• To drive process, methodology, innovations, efficiency gains in package design for feature development and resolve issues.
• Capable of working both individually and in cross-functional teams
• Enthusiastic and highly motivated to acquire new skills