Lead Analog Layout Design Engineer (SERDES)

Job Overview:

The Lead Analog Layout Design Engineer will take a senior role on the PMA custom layout design team as part of a SERDES Product Team located at Cork, Ireland.

Job  Responsibilities:

• Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)
• Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers
• Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules
• Work with Technical Team Leads in the areas of blocks layout design and PHY top levels
• Mentor Junior Layout Design Engineers when the project need arises
• Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications:

• Candidate’s background should include a minimum of 4 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
• Excellent layout design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
• Assist with the architecture and implementation of complete PHY gds with integration of PMA, PCS hierarchies and optimized clock and power distribution strategies
• Working with custom layout designers from groups all over the world to build high quality IP and test chips
• Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• BEng, MEng or PhD

Additional Skills/Preferences:           

• Cadence tool experience and design experience at >10Gbps and in <40nm technologies
• Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools