Junior Hardware Verification Engineer

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation. 

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter! 

At Arteris your role will be

Key Responsibilities:

• Define, document, develop and execute RTL verification test/coverage for extremely parameterized IPs in Python and C++, capable of running on any available RTL simulator (Cadence, Synopsys, etc.).
• Maintain and improve verification workflow, improve metrics and increase automation.
• Implement verification components such as BFMs or monsters. such as BFMs or monitors used in verification test benches.

Required Experience / Qualifications:   

• Understanding of hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog).
• Strong experience in the use and development of verification methods and infrastructure (VIPs, UVMs, testbeds, EDA tools).
• Experience in formal proof verification methodology is a plus
• Shell scripting
• Knowledge of interconnect technology is a plus
• Understanding of hardware communication protocols (AMBA, OCP, others)
• Good written and oral communication in French and English.
• Curious, autonomous, rigorous and results-oriented, with a commitment to quality and a thorough approach to work.
• Proven ability to work well in a team environment

Base Salary depending qualification and experience between 40 – 44 KE / year

Educational Requirements:

• Master’s degree or Doctorate in engineering or computer science