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Junior Design for Test Engineer

Junior Design for Test Engineer
by Admin on 11-02-2022 at 11:43 am

Website Menta

Job description

Within the Hardware DfT R&D team, you will be in charge of implementing DfT strategy for the IP – both FE and BE, with a mix of R&D and production work.

This is a challenging position and an opportunity to work within a small but highly qualified team. You will get the chance to work on one of the most exciting new semiconductor product and on the most advanced process nodes in a fast growing company.

The candidate needs to be passionate, innovative, keen to learn and able to commit on deliveries.

Desired skills and experience

  • MS or a PhD in Computer Science, Electrical Engineering or related discipline

  • A 1 to 2 years of experience in DfT definition and implementation is a plus (Scan insertion, Memory BIST, Test patterns generation and validation)

  • Knowledge in DFT and EDA tools such as Synopsys DFT-Compiler, DFT-Max, TetraMax, SMS and Siemens EDA Tessent is a plus

  • Knowledge of digital BE EDA tool flows required such as Synopsys ICC and PrimeTime is a plus

  • Experience with simulation tools such as Siemens EDA Questasim is a plus

  • Experience at IP level and IP integration at top level is a plus

  • Experience with make files and scripting languages such as Tcl, C++, Perl, Python and bash is a plus

  • FPGAs architecture and FPGAs software knowledge is a plus

  • Knowledge in RTL design (VHDL, Verilog, SystemVerilog) and/or RTL synthesis

  • Good written and spoken English is mandatory

The candidate will work in a dynamic environment and will get to work with teams from different technical areas in which new creative and innovative ideas are appreciated

Apply for job

To view the job application please visit www.menta-efpga.com.

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