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Junior and Senior Physical Design Engineer (ASIC/SoC Place & Route)

Junior and Senior Physical Design Engineer (ASIC/SoC Place & Route)
by Admin on 04-28-2022 at 3:00 pm

Website TSMC

· Perform the following:
o  Block level floorplan,
o  Clock tree synthesis,
o  Place & Route,
o  RC extraction,
o  STA, timing closure,
o  IR/EM analysis and fix,
o  DRC/LVS/ERC clean up,
o  Tape-out sign off.
o  Additional duties assigned by the supervisor
· Customer on-site support.
o  Bachelor/Master’s degree in Electrical Engineering or Computer Science.
· 3-20 years Netlist (or RTL)-GDS physical implementation experience.
· In depth knowledge of major EDA tools/design flows.
· Experience with TSMC N28 or below technology.
· Experience in block level implementation or chip integration and signoff.
· Experience in Perl/TCL language programming.
· Proven record in multi-million gate design production tapeouts.
· Proven ability to analyze issues, solve problems and bring closure
Quality of execution and follow-through – able to execute tasks assigned by the supervisor and customers and acquire the necessary skills to execute assignments.

Experience in any of the following is a plus:

o  TSMC N16 and below technology.
o  Low-power implementation methodology.
o  Advanced timing signoff methodology.
o  Able to independently complete Netlist-GDS P&R, signoff  task.
Required Competencies:
o Aggressive in learning and problem-solving.
o Self-motivated and able to work independently and collaborate with others – able to act in the company/team’s interest
o Proven ability to prioritize competing responsibilities and able to demonstrate multi-tasking skills
o Able to take the initiatives to resolve issues without waiting for others to call
o Strong ability to manage demands in a fast-paced environment and diverse
      cultural styles while being extremely adaptable and flexible.
o Strong attention to detail, communication and interpersonal skills.
Apply for job

To view the job application please visit

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