ISP ASIC Design Engineer

Design micro-architecture for image processing algorithms, spec definition, Block and top level RTL implementation, optimization and verification, Design flow and FPGA validation.

• Work experience and rank are not limited, master degree and above with related major, programming skills in Verilog HDL.
• Knowledge of Image or video processing.
• Experience of ASIC design (including specification, micro-architecture, and RTL implementation).
• Be familiar with design flow (Synthesis, Lint, CDC, DFT, and etc.).
• Experience of Image processor design, such as 3D noise reduction, HDR, white balance, image enhancer will be a plus.
• Highly motivated and skillful at solving difficult technical problems.