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IP/SOC Design Methodology and Flows Engineer

IP/SOC Design Methodology and Flows Engineer
by Admin on 10-31-2022 at 1:22 pm


Job Description

The PSG Structured ASIC Engineering Group (PSAE) within Intel Programmable Solutions Group is seeking exceptional talent for an IP SoC FE Design Methodology and Flows Engineer to work with a diverse team designing Intel next generation Custom Structured ASIC (Intel eASIC) based SOCs and Customer Design solutions – someone who is passionate to improve the way we solve complex problems through teamwork or direct contributions.

The IP Solutions team within PSAE is responsible for delivering IP-solutions for Customer designs on Structured ASIC (eASIC) demonstrating high quality RTL development, IP delivery and integration into SOCs, verification with all the IP Quality checks and Physical Convergence with the Structured ASIC device architecture and technology.

We are looking for a talented Front End Design Methodology Engineer to join our team. In this position, you will work on RTL design, integration and quality checks related flows across clusters, IP, Subsystems, SOCs. You will rapidly take features from concept to production and provide customer support, debug failures, and provide out of the box solutions.


*Understand and enhance the frontend design flows and methodologies across IPs and SOCs to identify key areas of improvement
* Provide user friendly solutions, to increase productivity of team
*Identify, define and publish the best practices for the various aspects related to RTL development, IP delivery, SOC integration, quality checks and back-end handoff
* Influence project execution and methodology while working with both external and internal tool vendors.
* Develop and deploy highly productive and robust build, run, and flow management environments and systems.
* Develop and deploy scripts and automations to assist the design and validation teams.
*Develop, deploy and mentor tool usage methodologies.


* Bachelor or Master’s degree in Computer Science, Electrical or Computer Engineering or related degree.
* 3+ Years of experience with system Verilog and familiarity with a range of internal and 3rd-party logic design tools
* 3+ years of experience in FE development flows and tools (Verilog design language, VCS, SpyGlass etc.)

* 3+ years developing enterprise-class programs, scripts and systems

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