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Sr. Design Verification Engineer

Sr. Design Verification Engineer
by akshay.vijaykumar on 04-14-2022 at 10:38 am

Primary Function of Position:

Verification of FPGA’s on daVinci systems for RTL functional correctness.
Roles & Responsibilities:

Responsibilities includes starting from testplanning to closing verification using coverage metrics.
Involves testbench development from scratch or modification to existing testbench infrastructure for verifying new features.
Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model.
Directed/constrained random test generation, failure analysis and resolution, coverage analysis.
Debugging failures, bug tracking, and analyze and close coverage.

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