Intern (Technical-Engineering)

We’re looking for a B.Tech/M.Tech/M.S college graduate and/or VLSI trained engineer to join our team as a technical intern.   Good academics and commitment to learn is a must ! Prior experience on ASIC Design/Verification is a plus !!

Are you agile to learn and contribute — Come, and be part of a collaborative team, environment, that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs.

This position is based in Bangalore, India.

In this role,

—   you will have a steep learning curve understanding the Synopsys DesignWare Interface IP Subsystem solutions, while contributing to the Design/Verification aspects.
—   you will have a chance to learn Verilog/System Verilog languages, RTL coding / integration of sub-modules.
—   learning and contributing towards the Verification of Subsystem designs.
—   exposure to DDR, PCIe, Ethernet and other interface protocols.
—   exposure to the front-end Implementation / Verification flows.
—   exposure to scripting, packaging of Subsystems.

Requirements :

—  Masters or Bachelors degree in Electronics engineering.
—  Good academics and commitment towards learning and accomplishing the project goals.
—  Be agile to learn fast and start contributing quickly.
—  Flexibility to learn and work on either Design or Verification tasks.
—  Good Communication and interpersonal skills.