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Intern software development for Verilog-A simulator

Intern software development for Verilog-A simulator
by Admin on 12-09-2022 at 2:04 pm

  • Internship
  • Beijing, China
  • Applications have closed

Website Cadence

– Familiar with Spice, Verilog-A, Verilog-AMS language
– Skilled in Python programming, familiar with development under Linux/Unix environment.
– Analog circuit or digital simulator development experiences is a plus
– Good mathematic background & knowledge is a plus
– Be familiar with Analog Mixed-signal design is a plus
– EE or CS Master degree with related working experience

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