Intern – Fall 2020 – Reliability Modeling

This intern/co-op position is for reliability modelling using Cadence RelXpert and other tools.  The candidate will work on improving the quality and efficiency of reliability/aging methodology and QA for advanced CMOS processes.

• Infrastructure development/enhancement for deployment and QA methodologies of aging models
• Aging production model release support
• Model hardware correlation generation methodology

Required Qualifications:        

• Education – PhD or Masters student in Electrical Engineering or Physics or other related disciplines
• Experience – Prior experience not required
• Travel – 0% of travel required
• Language Fluency – English

Preferred Qualifications:

• Knowledge in CMOS device physics
• Good programming skills with Python and Unix shell scripts
• Familiarity with SPICE level simulation (HSPICE, SPECTRE) is a big plus
• Familiarity with RelXpert (Cadence aging tool) is a big plus
• Good communication and team collaboration skills

Hiring Manager:  Jung-suk Goo

Intern or Co-Op: Intern (3+ months)

Dept:  Design Enablement

External / Internal:  External