In this role you will be a key member of a team participating in the design of a future generation Intel Atom microprocessor. This position requires an Engineer with a broad array of design skills, strong communication skills, and a desire to work effectively as part of a team of experienced engineers.
We are looking for a talented individual to drive implementation of standard cell-based design blocks from synthesis through post-layout verification and tapeout. You will develop the custom constraints for driving synthesis and auto-place and route (APR) tools to implement and optimize the design. You will work closely with the micro-architecture, RTL and custom circuit teams to converge the design to project targets.
Responsibilities for this position will include but not be limited to:
Critical path analysis and identification of logic structures requiring custom design and layout for timing optimization
Clock tree synthesis
RTL to gate level netlist generation through synthesis, placement, clock tree synthesis and route flows
Static timing analysis and convergence flows
Validation of physical design including timing, electrical rules, DRC/LVS, Noise, electro migration checks.
Formal equivalence verification
Scripting to automate tasks and improve debug efficiency
In addition to the qualifications listed below, the ideal candidate will demonstrate the following traits:
Willingness to work well in a team and be productive under aggressive schedules
Excellent written and verbal communication skills
Self-motivation and well organized
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have a Bachelors degree in Electrical/Computer Engineering and 6+ years of experience in: – OR – a Masters degree in Electrical/Computer Engineering and 4+ years of experience in:
Synthesis, APR and Timing tools and flows
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise, and electro-migration checks
Primetime, PTSI, Conformal LEC, RedHawk, Caliber, Spyglass LP
Perl and/or TCL coding
4+ years of industry experience/exposure with:
Physical design best known practices concerning floor-planning, routing techniques, clock distribution.
RTL-netlist methodologies and formal equivalence
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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To view the job application please visit jobs.intel.com.